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| WEDNESDAY, June 9, 2004, 8:30 AM - 10:00 AM | Room: 6B | ||
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TOPIC AREA: SYSTEM-LEVEL DESIGN AND VERIFICATION | ||
| SESSION 17 | |||
| Panel: Verification, What Works and What Doesn't | |||
| Chair: Robert Damiano - Synopsys, Inc., Hillsboro, OR | |||
| Organizers: Francine Bacchini | |||
| Today's leading chip and system companies are faced with ever increasing design verification challenges; industry studies revealing that as much as 50% of the total schedule is being spent in verification. Large companies, with almost infinite resources, have shown that throwing CPU cycles and people at the simulation problem still doesn't guarantee a level of coverage desired by the design team. So, what is the answer? Are assertions, faster simulators, and testbench languages the "holy grail", or are those just micro-optimizations of a methodology that is fundamentally flawed? Is there hope for a verification methodology that completely covers a design with a predictable verification schedule?
The panelists will describe their experiences of what works, and what doesn't, providing insights into their methodologies and philosophies. | |||
 17.1 |
Verification, What Works and What Doesn't |
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| Speaker(s): | Bob Bentley - Intel Corp., Makoto Ishii - Sony Corp., Osaki Shinagawa-Ku, Japan Einat Yogev - Cisco Systems, Inc., San Jose, CA Kurt Baty - WSFDB Consulting, Austin, TX Kevin Normoyle - Azul Systems, Inc., | ||
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